Comparative Analysis of 6T, 7T, 8T, 9T, and 10T Realistic CNTFET Based SRAM
نویسندگان
چکیده
منابع مشابه
A Comparative Study of 6T, 8T and 9T SRAM Cell
From the last few decades, the scaling down of CMOS devices have been taking place to achieve better performance in terms of speed, power dissipation, size and reliability. The major area of concern in today‟s CMOS technology is Data retention and leakage current reduction. SRAM (Static Random Access Memory) is memory used to store data. Conventional Static Random Access Memory (SRAM) cells suf...
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As the technology is improving , channel length of MOSFET is scaling down. In this environment stability of SRAM becomes the major concern for future technology. Static noise margin (SNM)[1] plays a vital role in stability of SRAM[2]. This paper gives an introduction to the “8T SRAM cell”[3]. It includes the Implementation, characterization and analysis of 8T SRAM cell and its comparison with t...
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In the world of Integrated Circuits, Complementary Metal–Oxide– Semiconductor (CMOS) has lost its credentiality during scaling beyond 32nm. Scaling causes severe Short Channel Effects (SCE) which are difficult to suppress. As a result of such SCE many alternate devices have been studied. Some of the major contestants include Multi Gate Field Effect Transistor (MuGFET) like FinFET and Carbon Nan...
متن کاملDesign Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential
As process technology is scaled down, a large-capacity SRAM will be used. Its power must be lowered. The V th variation of the deep-submicron process affects the SRAM operation and its power. This paper compares the macro area, readout power, and operating frequency among dual-port SRAMs: an 8T SRAM, 10T single-end SRAM, and 10T differential SRAM considering the multi-media applications. The 8T...
متن کاملVIPUL BHATNAGAR et al: ANALYSIS OF SRAM BIT CELL TOPOLOGIES IN SUBMICRON CMOS
The paper investigates on the design aspects of different SRAM cells for access time, power consumption and static noise margin. All the designs are made by using standard 90nm CMOS process. Simulations have been done for 6T, 7T, 9T and 10T SRAM cells. 10T SRAM cell shows the best SNM among all the simulated cells. 9T shows least power and least access time. 6T cells stability limits the potent...
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ژورنال
عنوان ژورنال: Journal of Nanotechnology
سال: 2017
ISSN: 1687-9503,1687-9511
DOI: 10.1155/2017/4575013